1. Field of the Invention
This invention relates in general to the fabrication of integrated circuit (IC) devices, and more particularly to a method for fabricating metal oxide silicon (MOS) devices with reduced anti-punchthrough regions for use in connection with scaled-down manufacture process.
2. Description of the Prior Art
In submicron sized transistors, hot electron injection into the gate of such transistors is a serious reliability problem. Structures have been proposed to overcome this problem in the attempt to design a high speed very large scale integration (VLSI) manufacturable submicron MOS transistor which exhibits resistance to hot electron degradation.
One such device is a MOS device with anti-punchthrough region. The fabrication process for making this device will be better understood from the following detailed description by referring to FIGS. 1A to 1C.
As shown in FIG. 1A, a field oxide layer 11 is formed by the conventional local oxidation of silicon (LOCOS) process to define an active area on a P type silicon substrate 10. A pad oxide layer 12 and a silicon nitride layer 13 are sequentially formed by chemical vapor deposition (CVD) on the silicon substrate 10. The pad oxide layer 12 and the silicon nitride layer 13 are patterned by conventional lithography and etching processes to form an opening 8 which exposes the area of the silicon substrate 10 that will form a gate electrode. A P.sup.+ anti-punchthrough region 14 is then formed by implanted boron ions through the opening 8 into the silicon substrate 10.
Turning now to Fig. 1B, a gate oxide layer 15 is formed on portion of the silicon substrate 10 within the opening 8. A polysilicon layer 16 is deposited by CVD overlying the gate oxide layer 15 and the silicon nitride layer 13. Next, the portion of the polysilicon layer 16 over the silicon nitride layer 13 is removed, such as by chemical mechanical polishing (CMP), so as to provide a generally planar surface, as is shown in FIG. 1C. The remaining portion of the polysilicon layer 16 within the opening 8 forms a polysilicon gate 16a. The gate oxide layer 15 and the polysilicon gate 16a together define a gate electrode.
The silicon nitride layer 13 and the pad oxide layer 12 are then removed by etching. N type impurities, such as phosphorous ions, are implanted into the P type silicon substrate 10 to form N.sup.- lightly doped source/drain regions 18 by using the polysilicon gate 16a as a mask. Next, a sidewall spacer 17 is formed on each the sidewall of gate electrode, i.e., the polysilicon gate 16a and the gate oxide layer 15, by deposition and an etching back process well known in the art. Finally, N type impurities, such as arsenic ions, are implanted into the P type silicon substrate 10 to form N.sup.+ heavily doped source/drain regions 19 by using the polysilicon gate 16a and the sidewall spacers 17 as a mask, completing the fabrication of prior art MOS device.
The above prior art MOS device uses a P.sup.+ anti-punchthrough region 14 formed beneath the gate electrode and between the source/drain regions to prevent the hot electron effect, thereby improving the device reliability. However, with the continued reduction of the size of devices, the relatively high contact resistance of the source/drain regions becomes a major drawback when applying this technique to submicron processes. In addition, due to the limitation in the configuration of the prior art device, the process step of forming metal contacts should be performed in the area above the N.sup.+ heavily doped source/drain regions 19. Therefore, it is difficult to make further reductions in the size of the device.
It is therefore an object of the present invention to provide a method for fabricating MOS device capable of preventing the hot electron effect and reducing the contact resistance of the source/drain regions.
It is another object of the present invention to provide a method for fabricating MOS device, which can significantly reduce the device size so that it is suitable for use in submicron processes.